In synchronous DRAM applications, the output buffer comprises a NMOS pull-up transistor and a NMOS pull-down transistor. ESD protection needs to be provided at this output buffer without the use of any protection device that would require a series resistor due to the high speed requirements of the device. The synchronous DRAM is designed to operate at greater than 60 MHz, so switching of the outputs high and low is critical. Any resistance in the speed path will slow down the output driver. Furthermore, a protection scheme that works for both positive and negative stress polarities is beneficial.
One prior art output protection scheme used in logic applications is shown in FIG. 1. This scheme uses a pull-up PMOS transistor 20 to power the dummy protection transistor 22 during an ESD pulse. The dummy protection transistor 22 is connected in parallel with the output NMOS transistor 24 and has a gate tied off (i.e., to 0V) with Vcc power up through PMOS transistor 20 and a source tied to a grounded substrate. The pull-up PMOS provides automatic protection to Vcc. In other applications, the gate of transistor 22 is directly connected to ground.
Unfortunately, in DRAM applications, a PMOS pull-up is not available to power up Vcc during ESD. The prior art dummy transistor relies on the PMOS pull-up for its operation during ESD. Furthermore, without the pull-up PMOS, there is no automatic protection to Vcc. Finally, for floating substrate DRAMs, there is no diode to substrate and if the gate of the protection is not properly controlled or is grounded, the ESD level will be lower for negative stress polarities. It is now well known that ESD protection levels in a multi-finger NMOS transistor can become erratic when a grounded gate protection device is used.
Accordingly, a protection scheme that is more appropriate for floating substrate DRAMs, as well as one that can be extended to grounded substrate technologies, is desired.